1. Field of the Invention
The present invention relates to a circuit designing apparatus for feeding test vectors in the circuit description defining the structure and specification of the circuit to be designed, comparing the output signal and an expected value of output signal to verify the logic of the circuit description, and fabricating an actual circuit by using this circuit description, a circuit designing method, and a computer-readable recording medium storing a circuit designing program, and more particularly to a technique of shortening the time required for logic verification of circuit description so as to curtail the time and expense required for circuit design processing substantially.
2. Description of the Related Art
At the present, in a general circuit designing process, first, a circuit description defining the structure and specification of a circuit to be designed is prepared, and after judging the validity of the circuit description, a mask pattern is made from the circuit description, and an actual circuit is fabricated.
One of the techniques for judging the validity of the circuit description made in this circuit designing process is a process known as logic verification (for example, function verification, timing verification, and the like) for checking if the function of the circuit to be designed is realized according to the specification or not. In logic verification process, plural test vectors compiled by each function desired to be checked by the designer are fed into the circuit description, and the output signal and an expected value of output signal are compared. If the output signal and its expected value are different, it is judged that the circuit description includes some inconvenience, and the defective position in the circuit description is corrected so as to realize a desired function.
However, this conventional logic verification process involves the following technical problems.
That is, usually, if any defect is detected in the circuit description by logic verification process, the defective position in the circuit description is corrected, but generally when the circuit description is changed, in order to check if a new unexpected bug (defective point) is mixed in by change, or check if the specification realized before is similarly realized after change, regardless of the content of change, it is necessary to process logic verification again by using all test vectors previously used in the logic verification process, and therefore in the conventional logic verification process, the time required for logic verification increases in proportion to the number of times of change of circuit description, possibly leading to a significant delay in the term of circuit designing process.
Besides, as the circuit to be designed is large in scale and complicated, the logic verification time required for one test vector is very long, and by the increase of the required verification items, the number of test vectors required for logic verification increases, and henceforth as the circuit becomes larger in scale and more complicated, such technical problems evidently become more and more serious.